This invention relates to the field of ceramic chip carriers for semiconductor chips, and particularly to such carriers of the so-called "leadless" variety.
It has become common practice in the microelectronics art to package a silicon chip integrated circuit ("chip") in a recess formed in a surface of a ceramic substrate. A plurality of electrical leads are formed onto the substrate surface, as by masking or screen printing, to provide conductive paths between the terminals of the integrated circuit and external contacts. One type of ceramic substrate with its metallized conductive leads terminating at the four sides of the substrate is commonly referred to as a "chip carrier".
One specific chip carrier design which is becoming increasingly popular is the so-called "leadless" carrier, an example of which is disclosed in U.S. Pat. No. 4,288,841 to Gogal. This type of carrier lacks discrete external leads for providing electrical paths from the metallized internal leads or "traces" on the substrate surface. Rather, these metallized traces are continued along the side edges of the substrate to provide side metallizations which are contacted by contact members in a socket. As shown in the aforementioned Gogal patent, these side metallizations are provided in vertical grooves or "castellations" formed in the peripheral edges of the substrate.
The use of leadless chip carriers has been limited, however, by a lack of any inherent means for the prevention of damage to the chip from static electricity during installation of the chip in the carrier, a phenomenon known as "zapping". Leaded carriers avoid this problem by use of lead frames in which the lead members are interconnected by a frame member called a "tie bar" or "shorting bar", which provides a shunt for static discharge induced currents. The shorting bar is then removed when installation and burn-in of the chip are completed. See, for example, U.S. Pat. No. 3,999,285 to Lewis et al.; U.S. Pat. No. 4,141,712 to Rogers; and U.S. Pat. No. 4,362,902 to Grabbe. Leadless carriers, however, lack a lead frame structure with which conventional shorting bars can be used, and no suitable substitute has been available.
Thus, it would be advantageous to provide some means, in a leadless chip carrier package, for reducing or eliminating the hazard of "zapping" the chip. It would also be advantageous to provide such protection in a manner which is easily adaptable to the mass production techniques employed in fabricating such devices.